apl. Prof. Dr. Wolfgang Müller
- E-Mail:
- wmueller@hni.uni-paderborn.de
- Phone:
- +49 5251 60-6352
- Web:
- Homepage
- Office Address:
-
Fürstenallee 11
33102 Paderborn - Room:
- F0.431
Publications
Latest Publications
Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations
K.A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, in: 38. ITG / GMM / GI - 威尼斯人官网 Testmethoden Und Zuverl?ssigkeit von Schaltungen Und Systemen, Potsdam, 2026.
TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture
K.A. Hannemann, L.M. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, J.C. Scheytt, in: 29. 威尼斯人官网 Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026), 2026.
Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells
L. Luchterhandt, V. Govindasamy, Y. Wang, R. D?mer, W. Müller, J.C. Scheytt, in: OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits, Lyon, France, 2025.
60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design
B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025).
A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology
M. Iftekhar, B. Sadiye, W. Müller, J.C. Scheytt, in: IEEE Nordic Circuits and Systems Conference (NORCAS), 2025.
Show all publications
Teaching
Current Courses
- VLSI Testing
- VLSI Testing
- Topics in Systems Engineering - IC Design
- Projekt Angewandte Programmierung
- Electronic System Design (Project)
- Electronic System Design (Project)
- Advanced VLSI Design
- Advanced VLSI Design